Computer System Architecture MCQs

 Enhance your understanding of computer system architecture through challenging multiple-choice questions (MCQs) covering key topics such as CPU organization, memory management, system design, input-output organization and parallel processing etc. Our MCQs are ideal for students, professionals and any one interested in mastering computer architecture. Start exploring now...

1. Combinational logic circuits implement-

  A.  Boolean functions

  B.  Arithmetic functions

  C.  Both A and B

  D.  None of these

2. Digital circuits are-

  A.  Combinational and sequential

  B.  Wired and wireless

  C.  Manual and automatic

  D.  None of these

3. A multiplexer is also known as -

  A.  Coder

  B.  Decoder

  C.  Data selector

  D.  Multi-vibrator

4. The multiplexer is a-

  A.  Single logic device

  B.  Combinational logic switching device

  C.  Either single or combinational logic device

  D.  None of these

5. A two variable function has ...... possible minterms.

  A.  Two

  B.  Four

  C.  Seven

  D.  Eight

6. RS latch have two inputs S and R. S is called set and R is called-

  A.  Restart

  B.  Reset

  C.  Revoke

  D.  Renew

7. In asynchronous sequential circuit-

  A.  Output depends upon users desire

  B.  Output depends upon the order of input

  C.  Both A and B

  D.  None of these

8. The synchronous sequential circuit-

  A.  Uses semiconductor for storage 

  B.  Uses flip-flops for storage

  C.  Uses hard disk for storage

  D.  None of these

9. The state table is same as the excitation table of a-

  A.  Transistor 

  B.  Flip-flop

  C.  Semiconductor

  D.  None of these

10. Simplify the boolean function xy + xy' algebraically -

  A.  1

  B.  x

  C.  y

  D.  None of these

11. Σm(1,2,4,6) is equivalent to -

  A. ΠM(0,3,4,5,7)

  B. ΠM(0,3,4,7)

  C. ΠM(0,3,6,7)

  D. ΠM(1,2,4,6)

12. A flip-flop can store-

  A.  One bit of data  

  B.  Two bits of data

  C.  Three bits of data

  D.  Any number of bits of data

13. The output of sequential circuit depends on-

  A.  Present input only  

  B.  Past input only

  C.  Both present and past inputs 

  D.  Present output only

14. Parallel adders are-

  A.  Combinational logic circuit  

  B.  Sequential logic circuit

  C.  Both (A) and (B) 

  D.  None of the above

15. The two input XOR gate has a high output only when the input bits are-

  A.  Even  

  B.  Different 

  C.  High 

  D.  Low

16. The number of control lines for a 8:1 MUX is-

  A.  2

  B.  3 

  C.  4 

  D.  5

17. How many flip-flops are required for mod-16 counter?

  A.  6

  B.  3 

  C.  4 

  D.  5

18. The gates required to build a half adder are-

  A.  Ex-OR gate and NOR gate

  B.  Ex-OR gate and OR gate

  C.  Ex-OR gate and AND gate 

  D.  Four NAND gates

19. A device which converts BCD to seven segment, is called-

  A.  Encoder

  B.  Decoder

  C.  Multiplexer 

  D.  Demultiplexer

20. An OR gate can be imagined as -

  A.  Switches connected in series

  B.  Switches connected in parallel

  C.  MOS transistors connected in series 

  D.  All of the above

21. A shift register can be used for -

  A.  Serial to parallel conversion

  B.  Parallel to serial conversion

  C.  Digital delay line 

  D.  All of the above

22. The number of full and half adders required to add 16bit numbers are -

  A.  8 half adders, 8 full adders

  B.  1 half adders, 5 full adders

  C.  16 half adders, 0 full adders 

  D.  None of these

23. The main difference Between J-K and R-S flip-flops is that -

  A.  J-K flip-flop does not need a clock pulse

  B.  There is a feedback path in J-K flip-flop

  C.  J-K flip-flop accepts both inputs as 1 

  D.  J-K flip-flop is acronym of junction cathode multivibrator

24. A ring counter consisting of five flip-flops will have -

  A.  5 states

  B.  10 states

  C.  32 states 

  D.  Infinite states

25. How many full adders are required to construct a m-bit parallel adder ?

  A.  m/2

  B.  m-1

  C.  m+1

  D.  m

26. RISC stands for -

  A.  Reduced instruction set computer

  B.  Reverse instruction set computer

  C.  Reduced implied set computers

  D.  Reverse implied set computers

27. The mode in which effective address is equal to address part of instruction is -

  A.  Direct addressing mode

  B.  Indirect addressing mode

  C.  Regiser addressing mode

  D.  None of these

28. ADD R1, A, B is -

  A.  Zero address instruction format

  B.  One address instruction format

  C.  Two address instruction format

  D.  Three address instruction format

29. SP stands for -

  A.  Storage pointer

  B.  Stack pointer

  C.  Synchronous pointer

  D.  None of these